1. Field of the Invention
The present invention relates to increased density electronic products, and in particular to high performance area array integrated circuit (IC) packages designed to achieve maximal component density and improved performance via the incorporation of integral layers such as built-in capacitive decouplers and termination resistances within an interconnect substrate of the IC package.
2. Description of the Related Art
The density of electronic products is increased by assembling ICs into smaller packages. Ideally, such packages are also low cost and provide high performance, electrical testability and environmental protection for the ICs.
The density of an IC package can be measured by the ratio of the area ("footprint") it consumes on a printed wiring board to the area of the actual silicon chip in that package. The present invention pertains inter alia to the reduction of this footprint ratio without sacrificing the primary desiderata suggested above and enumerated in greater specificity as objectives (b)-(n) below.
Two general types of component packages exist at this time: 1. Perimeter Input/Output (I/O) surface mount packages, such as: (i) Very Small Outline Packages (VSOPs); (ii) Fine Pitch Quad Flatpacks (FPQFs); and (iii) Tape Automated Bonding (TAB).
2. Area I/O packages such as: (i) Pin Grid Arrays (PGAs); and Land Grid Arrays (LGAs).
Conventionally, both types of IC packages must be increased in size in order for passive components to be added thereto. As may be readily appreciated, there is a need for I/O packages which more closely approach an ideal package where the footprint ratio equals unity. Such an ideal IC package is characterized by a board footprint approximately equal to the size of the silicon chip.
Those skilled in the art of IC packaging currently pursue the design of a high performance IC package which is characterized by the following desirable attributes:
a. Overall dimension as close to the bare IC as possible (i.e. unity or nearly unity footprint ratio); PA1 b. Maximum Outer Lead Assembly Pitch (spacing), for optimal assembly yield and for ease of electrically testing at speed; PA1 c. Integral, low-inductance, power supply decoupling capacitance layers which reduce switching-induced noise and improve integrated circuit electrical performance; PA1 d. Integral resistance, capacitance layers patterned to provide individual integral components; PA1 e. Considerably reduced inductance between the integrated circuit and the decoupling capacitance over alternatives (i.e., discrete capacitors located inside or outside the body of the package); PA1 f. Environmental protection (i.e., encapsulation); PA1 g. Low assembled cost and ease of manufacturability; PA1 h. Reduce/eliminate requirements for discrete resistors or capacitors internal or external to the package; PA1 i. Provide values and tolerances of integral resistor and capacitor components that can not be manufactured in integrated circuit processes; PA1 j. Provide for resistor, capacitor values tuned to a specific die design integral to the package that extend the capability of the integrated circuit beyond what is possible in a single integrated circuit manufacturing process, (i.e., provide signal line termination and matching, provide analog circuits such as filters, provide mixed-signal or analog/digital functionality such as antenna matching within a single package approaching the form factor of the die); PA1 k. Provide extended capability by joining a separately optimized and manufactured substrate to the die; PA1 l. Reduced die area, cost, power and improved performance resulting from smaller optimized I/O drivers, lower package parasitics, terminated signalling or clock lines, reduced noise, reduced on-die power decoupling requirements; PA1 m. Support increased integrated circuit clock frequencies in a low-cost, small form factor, easy to assembly package; and PA1 n. Also optionally provide for integral inductance layers providing the ability to form individual low-loss inductor components to support filter design or transformers for applications such as wireless systems or other analog applications.
The presently disclosed IC package and method for manufacturing the same achieve the desideratum (a) of a footprint ratio close to unity and the other even more desirable performance enhancement goals (b)-(n) recited above.
Accordingly, an object of the present invention is to provide an apparatus and method for reducing the overall IC package footprint to that of the bare IC, thereby reducing printed circuit board (PCB) costs.
Another object is to provide an IC component package with a maximum outer lead bond (OLB) pitch, for optimal assembly yield and for ease of high speed electrical testing.
Still another object is to eliminate the need for associated passive components in an IC component package via integral layers including integral capacitive, resistive and inductive layers.
An additional object is to provide an IC component package that is manufacturable at low cost from plastic films or combinations of organics, such as ceramic/silicon, and organic films.
Another object is to provide an IC component package which is designed to withstand hostile environmental conditions.